1. Technical Field
The present invention relates to a semiconductor device.
2. Related Art
Conventionally, various elements are placed in the insulating layer interposed between the upper interconnects and the lower interconnects in a semiconductor device.
Examples of the elements are fuse elements and MIM capacitors.
Those elements are connected to vias in the insulating layers, and are connected to the upper interconnects and the lower interconnects through the vias (see Japanese Laid-Open Patent Publication Nos. 2003-273220 and 2004-128498, for example).
More specifically, as shown in FIG. 4, vias 901 penetrate through an element 900 (a fuse element in this example), and the element 900 is in contact with the side faces of the vias 901. The upper end portions of the vias 901 are connected to upper interconnects 902, and the lower end portions of the vias 901 are connected to lower interconnects 903.
In FIG. 4, reference numerals 904 through 906 indicate insulating layers.
However, the semiconductor devices disclosed in Japanese Laid-Open Patent Publication Nos. 2003-273220 and 2004-128498 have the following problems.
In the semiconductor devices disclosed in Japanese Laid-Open Patent Publication Nos. 2003-273220 and 2004-128498, the vias 901 penetrate through the element 900, and the contact areas between the vias 901 and the element 900 are small. Therefore, it is difficult to lower the contact resistance between the vias 901 and the element 900.
Further, in the semiconductor devices disclosed in Japanese Laid-Open Patent Publication Nos. 2003-273220 and 2004-128498, the vias 901 penetrate through the element 900. With this arrangement, it is necessary to form via holes that penetrate through the element 900, after the element 900 is formed. Etching is performed to form the via holes. However, the material forming the element 900 completely differs from the material forming an insulating layer 905. Therefore, the portions 900A of the element 900 exposed through the inner surfaces of via holes H might be etched during the etching process, as shown in FIG. 5. In this case, it is difficult to fill the etched portions 900A with the metal forming the vias 901. As a result, there might be variations in the contact resistance between the vias 901 and the element 900, or the contact resistance might become higher.
As described above, conventional semiconductor devices are poor in manufacturing stability.